Pipelining in VHDL (3 stage)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity accum is
port (
clk : in std_logic;
rst : in std_logic;
port0 : in std_logic_vector (7 downto 0);
port1 : in std_logic_vector (7 downto 0);
port2 : in std_logic_vector (7 downto 0);
port3 : in std_logic_vector (7 downto 0);
port4 : in std_logic_vector (7 downto 0);
port5 : in std_logic_vector (7 downto 0);
port6 : in std_logic_vector (7 downto 0);
port7 : in std_logic_vector (7 downto 0);
portout : out std_logic_vector (10 downto 0));
end entity;

— 3 stage pipeline
architecture loop_imp4 of accum is

type capture_t is array (0 to 7) of signed (10 downto 0);
signal capture_s : capture_t;

signal capture_sum_v_1 : signed(10 downto 0);
signal capture_sum_v_2 : signed(10 downto 0);
signal capture_sum_v_3 : signed(10 downto 0);
signal capture_sum_v_4 : signed(10 downto 0);

begin

process (clk, rst)

begin

if (rst = ‘1’) then
capture_s <= (others => (others => ‘0’));
elsif (rising_edge (clk)) then

capture_s(0) <= to_signed(to_integer(signed(port0)), 11);
capture_s(1) <= to_signed(to_integer(signed(port1)), 11);
capture_s(2) <= to_signed(to_integer(signed(port2)), 11);
capture_s(3) <= to_signed(to_integer(signed(port3)), 11);
capture_s(4) <= to_signed(to_integer(signed(port4)), 11);
capture_s(5) <= to_signed(to_integer(signed(port5)), 11);
capture_s(6) <= to_signed(to_integer(signed(port6)), 11);
capture_s(7) <= to_signed(to_integer(signed(port7)), 11);

capture_sum_v_1 <= capture_s(0) + capture_s(1);
capture_sum_v_2 <= capture_s(2) + capture_s(3);
capture_sum_v_3 <= capture_s(4) + capture_s(5);
capture_sum_v_4 <= capture_s(6) + capture_s(7);

portout <= std_logic_vector(capture_sum_v_1 + capture_sum_v_2 + capture_sum_v_3 + capture_sum_v_4);

end if;
end process;
end loop_imp4;